In a conventional TFT LCD (thin-film transistor liquid crystal display), a pixel is comprised of a thin film transistor, a liquid crystal capacitor (Cp) and a storage capacitor (Cst). The transistor serves as a switch for the voltage applied to the liquid crystal capacitor. In the turn-on duration of the transistor, the liquid crystal capacitor is charged by a gray voltage corresponding to a color signal in the pixel. The storage capacitor may be connected to the liquid crystal capacitor in parallel, thereby preventing the charged voltage across the liquid crystal capacitor from leaking out during the turn-off duration of the transistor. In such a TFT LCD, the voltage for turning on the TFT is called "gate-on" voltage, and the voltage for turning off the TFT is called "gate-off" voltage. In actual applications, the gate-on voltage is more than 20V, and the gate-off voltage is less than -7V. As the liquid crystal panel becomes larger and has higher resolution, a gate on/off voltage having a larger DC level is typically required. In the TFT LCD, the voltage charged in the liquid crystal capacitor controls the transmittance of the light passing through the liquid crystal in the corresponding pixel, and thus a color display is formed.
FIG. 1 shows a typical current-voltage characteristic of a TFT. Referring to FIG. 1, when the voltage Vgs between gate and source of a TFT is Von, a current flows through the TFT to cause the voltage at source electrode (e.g., data line) to be applied to the liquid crystal capacitor. When the voltage Vgs is Voff, current through the TFT is greatly restricted to a level loff, thereby preventing leakage of the charge stored in the liquid crystal capacitor. On the other hand, when the voltage Vgs is 0V, a low level current flows through the TFT to discharge the liquid crystal capacitor.
A conventional TFT LCD will now be described in connection with the attached drawings. As shown in FIG. 2, a TFT LCD includes a timing control circuit 1, a gate driving circuit 2, a source driving circuit 3, a gray voltage generator 4, a liquid crystal panel 5 and a gate on/off voltage generator 6. The timing control circuit 1 receives color signals RGB, horizontal and vertical synchronization signals Hsync and Vsync and a clock signal CLK. The output of the timing control circuit 1 is supplied to the gate driving circuit 2 and the source driving circuit 3. The gray voltages produced from the gray voltage generator 4 are supplied to the source driving circuit 3. The gate on/off voltages Von and Voff produced by the gate on/off generator 6 are supplied to the gate driving circuit 2. The liquid crystal panel 5 is comprised of a plurality of gate lines G0-Gn, a plurality of data lines D0-Dn which cross the gate lines and a plurality of pixels. The gate lines G0-Gn are connected to the gate driving circuit 2, and the data lines D0-Dn are connected to the source driving circuit 3. Each pixel is defined by the gate and the data lines, and has a TFT, a storage capacitor Cst and a liquid crystal capacitor Cp. The gate of the TFT is connected to a gate line, and the source of the TFT is connected to a data line. The liquid crystal capacitor (Cp) and the storage capacitor (Cst) are connected to the drain of the TFT. The liquid crystal capacitor and storage capacitor may be connected in parallel. However, a common electrode voltage (Vcom) may be applied to the opposite terminal of the liquid crystal capacitor and the opposite terminal of the storage capacitor may be connected to a previous gate line, as illustrated. Accordingly, the voltage across the liquid crystal capacitor is determined by the voltage difference between the common electrode voltage (Vcom) and the data line voltage and the voltage across the storage capacitor is determined by the voltage difference between the data line voltage and the previous gate line voltage. In such a panel structure, no pixel is connected to the first gate line G0. As will be understood by those skilled in the art, such a panel structure has a high opening ratio since it does not require additional lines to obtain the storage capacitance. For this reason, the illustrated TFT LCD panel structure is widely used.
In FIG. 2, the timing control circuit 1 controls the timing of the color signals RGB and generates control signals to operate the driving circuits 2 and 3. The gray voltage generator 4 produces a plurality of gray voltages, and the gate on/off voltage generator 6 produces gate-on and gate-off voltages. The gray voltages are supplied to the source driving circuit 3, and the gate-on and the gate-off voltages are supplied to the gate driving circuit 2. By using the gate on/off voltage and the output of the timing control circuit 1, the gate driving circuit 2 generates gate driving voltages that enable each row of pixels to be turned on sequentially for one horizontal scanning time. These gate driving voltages are applied to corresponding gate lines. The one horizontal scanning time interval is defined as the time to be taken in applying data driving voltages to all the pixels connected to one gate line. The source driving circuit 3 selects one of all the gray voltages in accordance with the color signals RGB which are inputted sequentially from the timing control circuit 1, and applies the selected gray voltage onto the corresponding data line. Then, each data line voltage is transferred to a corresponding pixel.
FIG. 3 is a typical timing diagram of the gate driving voltage implemented in a TFT LCD having the structure of FIG. 2. As shown in FIG. 3, a gate line Gn-1 is in an on-state for one horizontal scanning time in a frame duration, and is in an off-state for the rest of the time in the frame duration. Each gate line is turned on sequentially. The operation of the liquid crystal panel in a gate on/off state will now be further described. For example, when a gate-on voltage is applied to the gate line G1 in FIG. 2, and gate-off voltages are applied to the other gate lines, all the TFTs connected to the gate line G1 are turned on by the gate-on voltage. Then, the data driving voltage in each data line D1-Dm is applied to the liquid crystal capacitor Cp1 and the storage capacitor Cst1 through the corresponding TFT which is turned on. Thus, the liquid crystal capacitor Cp1 are charged by a difference between the data driving voltage and the common electrode voltage (Vcom), and the storage capacitors Cst1 are charged by a difference between the data driving voltage and the gate-off voltage of the previous gate line G0. Because the voltage across the storage capacitor is typically larger than the voltage across the liquid crystal capacitor, charges from the storage capacitor are typically supplied to the liquid crystal capacitor. Accordingly, the liquid crystal capacitor can be held in a charged state even after the corresponding gate line voltage is removed.
However, when a user turns off a power switch or an interruption in the power supply occurs, the performance of the conventional circuit described above may be limited. For example, immediately before the power supply is removed from a TFT LCD, the voltage Voff is applied to the gate electrodes of most of the TFTs. Accordingly, even during the power off state, the charge stored in a liquid crystal capacitor may not be immediately discharged because the corresponding TFT connected thereto remains off. Furthermore, the liquid crystal in the panel can be degraded by the dc voltages which remain after the power supply is removed.